Memory devices are widely used in electronic devices, such as digital cameras and personal audio players, for storing digital data. Many different types of memory are available, each using a different fundamental technology for storing data, and the memory may be volatile or non-volatile memory. Resistive random-access memory (RRAM) including conductive-bridge random-access memory (CBRAM) and flash are examples of non-volatile memory.
In RRAM, a resistive memory cell switches from a high resistance reset state to a low resistance set state during a set pulse, in order to program a cell from a logic “0” to a logic “1”. This programming is achieved with an electric field inducing ionic migration from an ion reservoir layer to an insulating layer, causing a conductive filament or “bridge” to form. Once a filament forms, current may flow in the memory cell. Some minimum current (i.e., Iset_final) is sustained for a minimum time for the memory cell to become “well” set.
Iset_final is controlled since the memory cell may not be well set if insufficient current is utilized and which may result in the memory cell being unable to retain the programmed set state. However, use of too much current may result in the memory cell being overset where it may be too difficult or impossible to recover the memory cell to the reset condition. Accordingly, it is desired to provide Iset_final of a set programming operation within a window between Iset_min_final (lower current level for data retention) and Iset_max_final (upper limit to avoid overset).
Referring to FIG. 1A, two separate conventional approaches to controlling Iset_final of a resistive memory cell 1 are discussed. The first approach controls the gate of a selector or access transistor 2 associated with the memory cell 1 to be programmed to a set state and current source 8 is not present or not utilized. The gate of the transistor 2 may be regulated so that the transistor 2 acts as a ballast since the transistor 2 is positioned relatively close to the cell 1. The memory cell 1 is additionally coupled with a bit line 4 which has an associated bit line capacitance 5 and resistance 6.
However, referring to FIG. 1B, the transistor 2 is relatively small and variations of the current may be significant resulting in an Iset_final current which is not within the desired window for programming discussed above. More specifically, the current may exceed the maximum/upper limit where the memory cell 1 is overset and may not be capable of being returned to the high resistive state, or the current may be less than the minimum/lower limit where the memory cell is under set and not programmed to the low resistive state.
The current source 8 is used to implement the second conventional approach for programming the memory cell 1 to a set state. The current source 8 is a current mirror located on a global bit line at the program load circuits outside of the memory array and is used to provide a set program pulse to memory cell 1 to form the filament. Transistor 2 is over-driven and Iset_final is regulated by current source 8. The current source 8 may be implemented using relatively large devices which may be controlled to provide tighter DC current distribution compared with the use of transistor 2 discussed above.
However, referring to FIG. 1C, since the current source 8 is outside of the memory array, the current source 8 cannot prevent a transient current spike 9 resulting from the bit line capacitance 5 when the filament is formed. This current spike 9 is uncontrolled and may exceed Iset_max_final and overset the memory cell 1 or damage it.
At least some embodiments described below are directed towards memory systems and memory programming methods which provide programming of memory cells between different memory states and which may also be subsequently reprogrammed.